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The TSB-RD 5-level Neutral-Point-Clamped inverter model implements, as the name says, one leg of a 5-level NPC inverter with dead-time support.

This inverter model is part of a new generation of Time-Stamped Bridge (TSB) called TSB-RD, RD standing for Real Diodes. These TSB supports interpolation methods of previous generation of TSB. The high-impedance mode and rectifying mode are now implemented with real SPS diode or a combination of SPS switch and thyristors (which are enablable diode in fact). Compared with the previous generation of TSB which implemented high-impedance mode with a zero-current feedback loop, TSB-RD are generally more stable and work with RC snubber of higher impedance than previous generation of TSB.

Dead-time support:

Like previous generation of TSB, TSB-RD blocks supports dead-time smaller than simulation time step (as opposed to SPS inverter models).


Figure 1:  Five-Level NPC inverter circuit configuration

Figure 1 shows the configuration of a 5-level NPC inverter for one leg. Several legs can be sued to model a 3-phase 5-level inverter. In Figure 1, the ground is set by the user and not required to be placed in the middle point of the DC side.

The active switches and the diodes are modeled as a simple binary resistance with Infinite OFF resistance and very low ON resistance. Therefore, the IGBTs depicted in Figure 1 are no more than these binary switches.

TSB-RD recommended usage with SSN

The TSB-RD are built using real SPS switches, diode and/or thyristors. All 3-phase inverters have 3 internal SPS switches per leg and 9 switches for a 3-phase inverter therefore, which is close to the typical limit for pre-calculation methods in real-time systems. The TSB-RD inverters are therefore best used in conjunction with SSN and put each inverter in a unique SSN group.

Maximum PWM frequency and selected sample time

Standard mode : Fratio>10

As with all TSB-RD, this 5-level NPC inverter TSB-RD model can be used with excellent accuracy down to a  Fratio of 10, Fratio=Fsampling/FPWM where Fsampling is equal to the inverse of the model sample time Ts .

For example, with a simulation time step of 10 microseconds (Fsampling=100kHz), a PWM frequency of 10 kHz is just fine. This is well described in the example section below.

Extended mode, Fratio<10:

It is also possible to use TSB-RD model with low Fratio, below 10,  with very good accuracy. In this region of operation, the PWM components of the simulation will slowly vanish, leaving the fundamental components and harmonics to be fully observable.

The ARTEMiS demo ‘PV converter using T-type inverters using TSB-RD models’ (Ttype_TSB_2rates.slx) shows such an example in the extended operation region of the TSB-RD. This model runs with 20 kHz PWM at a sample time of 15 µs . One aspect of this model is that it is multi-rate: the power system model runs at 15 µs while the RT-Events Pulse generation runs at 1 µs to provide the equivalent of HIL read PWM pulse accuracy. The same HIL connected model can run at 15 µs only. See ref 2.

RC snubber usage with TSB-RD

A big deal occurred in the past with previous generation of TSB that required to add a large RC snubber to stabilize its operation in the no-pulse mode. This TSB-RD most typically can run with negligeable RC snubber or often none.

If the model is to be used in natural rectifying mode, a small snubber of C=0.1 µF and R=1000 Ohms (typical) may be required for stability, an impedance 100X greater than previous generation of TSB.

Many TSB-RD demos can run stably with almost no snubbers like the SSN JMAG Spatial Harmonic PMSM Drive that is stable with an R _only snubber of 1 MΩ. R_only snubbers are advantageous because they don’t add capacitive states to the system of equations of the electric circuit being simulated.



Switches Ron (Ohms): the internal switches and diode conduction resistance in Ohms.

Snubber resistance (ohms): the snubber resistance in Ohms.

Snubber Capacitance (F): the snubber capacitance in Farads.

Note: the snubbers are always ‘in circuit’ as they are modeled by SPS components, unlike the previous generation of TSB where snubber was in-circuit only during high-impedance mode.

Note: the model has no sample time. It is a discrete model running at the SPS selected sample time.

Input and Output signals

Simulink connection points:

g: the active switches (IGBT/GTO/MOSFET) gate input signals. The order of the gate signal  is 1,5,2,6,3,7,4,8 referring to Figure 1. The gate signals are Mean-Active-Duty (MAD) type with a value between 0 and 1 inclusively.

Example: a transition sequence of [ 1 , 0.3 , 0] means [gate ON, gate turned-on at 30% of the time-step, gate OFF])

Example: a transition sequence of [ 0 , 0.3 , 1] means [gate OFF, gate turned-on at 70% of the time-step, gate ON]), i.e. the MAD value depends on the transition type and is equal to the average ON time of the gate signal during the time step.

Physical Modeling connection points:

A: inverter output

V++, V+, Vn, V-, V--: DC-bus connection points.
 (Vn is the neutral connection point, only used as a reference point in the model)


The demo model TSB_RD_5levelNPC_Drive.slx is available in the ARTEMiS path. The demo model implements a simple 3-phase inverter with the 5-level NPC inverter with several options such as back-EMF or rectifying modes.

DC duty-cycle scan can be made by setting the Console ‘’frequence(Hz)’ port to 0 and connecting a ‘Ramp’ to the ‘mi’ (modulation index) port.

In the image below, we compare load current for TSB scan vs. native SPS model scan at a fixed time step of 10 microseconds and a PWM frequency of 10 kHz. It can be observed that the ‘TSB’ load current is smooth across all the range of duty cycle while the ‘SPS’ one behaves in a step manner. The figure also show the SPS at 4 us to show that this stepping effect gradually goes to zero when the time step is decreased.

This stepping effect is caused by the sampling effect of the PWM pulse at 10 µs. 10 kHz corresponds to a period of 100 µs and this is not a sufficient sampling (1/10 ratio) for accurate simulation normally. The time-stamping capacity of TSB-RD solves this problem very efficiently. This also works if the TSB-RD gate signals come from FPGA fast-sampling digital inputs (5-10 ns in Opal-RT systems) using Mean Average Duty method to compute the average duty of the digital input at each time step.

See also

SSN TSB-RD (2-level, 3-level NPC, 3-level T-type) Help page.


C. Dufour, J. Mahseredjian , J. Bélanger, “A Combined State-Space Nodal Method for the Simulation of Power System Transients”, IEEE Transactions on Power Delivery, Vol. 26, no. 2, April 2011 (ISSN 0885-8977), pp. 928-935

Dufour C., Palaniappan K., Seibel B.J. (2020) Hardware-in-the-Loop Simulation of High-Power Modular Converters and Drives. In: Zamboni W., Petrone G. (eds) ELECTRIMACS 2019. Lecture Notes in Electrical Engineering, vol 615. Springer, Cham. https://doi.org/10.1007/978-3-030-37161-6_2

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