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ARTEMiS (Advanced Real-Time ElectroMagnetic Simulator)


The ARTEMiS Guide block is the main discrete simulation parameter control block of ARTEMiS from which the different ARTEMiS solvers can be selected.


The following pane is normally empty in ARTEMiS 7.3+.

Mask of the ARTEMiS Guide Block


The ARTEMiS Guide block is used to discretize the linear part of the state-space system generated by the SimPowerSystem blockset (SPS). It implements a strictly fixed time step simulation of SPS schematics and offers an alternative to the Tustin discretization method of the SPS to increase numerical stability and precision. In contrast to the simulation technique of the SPS, the 'ARTEMiS Guide' block precomputes and discretizes all state-space matrices for all combinations of the switch topologies thus permitting hard real-time simulation.

Since v6, ARTEMiS offers a new simulation algorithm called State-Space Nodal (SSN), which combines the accuracy advantages of state-space methods together with the advantages of nodal methods with regards to switch management. Basically, there is no switch count limit with the SSN solver.

Since v6 also, the interpolation method has been changed to ’Inlined’ methods which are more efficient in terms of calculation and more easy to use. The interpolation methods are now active by default because of their simplicity.


General Tab

Sample Time (s)Sets the sample time for the fixed time step simulation of the electrical part of the SPS model. This sample time should be the same as the one entered in the SPS PowerGUI block.
Enable State-Space Nodal methodWhen checked, activates the use of SSN methods and solver in all SPS circuits. Since 7.2.1, this also applies to SPS circuits that do not have Nodal Interface Blocks (NIB), the circuit is considered as a 1-group SSN circuit, using the SSN solver.


The option Dynamic calculation of switch pattern matrix permutations is now obsolete in ARTEMiS. This option was provided in case of a large switch count within a state-space method. With SSN, this switch count limitation does not exist anymore.

The option RLC load substitution by Dynamic Load model is now obsolete. The option was provided to deal with some flaws in the SPS load flow routines. Since R2011B, SPS comes with a new load flow routine corrected these issues.

The option Use SPS continuous machine model is now obsolete.

State-Space Solver Options Tab

This option applies only to the parts of the model that don’t use the SSN solver.

Note: The state-space solver of ARTEMiS has now been replaced with the SSN solver, using the same solver code, but with a special case with a unique SSN group. All parts of the model are now discretized with the solver of the SSN tab.

Therefore, the State-Space Solver Tab will be normally empty, unless the SSN option is unchecked or if the flag ARTEMIS_USE_STATE_SPACE_SFUN=1 is set in the workspace.

State-Space discretization method

Sets the discretization method used by the ARTEMiS algorithm for the normal state-space system, not the one using the SSN method.

Four different methods are available: art5 (default), art3, art3hd and trapezoidal.

The art5 and art3 discretization methods are highly stable and very-accurate integration methods. Both are immune to numerical oscillations caused by switch operations in power networks. The art5 method is theoretically more accurate than art3, as it approximates the matrix exponential Taylor expansion to the 5th term, while art3 and trapezoidal approximate to the 3rd and 2nd terms, respectively.
The art3hd discretization methods a highly-stable method with good precision, especially in highly non-linear networks like the demo example provides with SPS called power_surgnetwork. mdl. The art3hd method is the only integration method capable of simulating the power_surgnetwork.mdl model with a time step greater than 90us.


These options apply to all parts of the model when the Enable State-Space Nodal method is checked even with pure state-space parts of the model unless ARTEMIS_USE_STATE_SPACE_SFUN=1 is set.

SSN solverType of solver used for the SSN method. The SSN algorithm solves a model as two parts: state-space groups connected in a nodal method. The state-space groups can be solved by state-space discretization similar to standard ARTEMiS (art5 solver, an order 5 matrix exponential approximant) while the nodal part can be solved by Trapezoidal, Backward Euler or Balanced-zero-hold, a mix of Backward and Forward Euler. The default method is Trapezoidal. Other methods are provided for help only. In the case of numerical oscillations at nodal connection points, the Art5 or Backward Euler method can provide a solution.
Disable SSN group iterationsSSN iterates the solution within each group normally. For example, if 2 IGBTs are in the same SSN groups, iterations are made to find the correct and coherent switch pattern at all time steps. This does not apply if the switch is in different SSN groups. This option disables the internal group iteration process. This can accelerate simulations in rare cases.
Enable SSN quasi-impulse switch event checkThis is an option in the SSN group iteration that should be left OFF normally. In rare case, it may improve the simulation accuracy. If a model simulation accuracy improves with this option ON, the user should consider using iSWITCH iterative models
SSN Groups maximum number of iterationsThis set a limit on the number of iteration within each SSN groups. See Disable SSN group iterations option.
Maximum number of iterations (iMOV and iSWITCH)This option controls the number of global SSN iteration when iMOV and iSWITCH models are detected inside an SSN model. This option only applies to iMOV and iSWITCH models. See Iterative Model in SSN section for more details.
Enable SSN node type verification

(new in ARTEMiS 7.1.0): Enable some verification routines related to SSN NIB type (V-type, I-type and in some case X-type). The underlying method first considers capacitors as short-circuits and inductors are open-circuits.

Basic rules are then derived:

  • V-type NIB should not have a low impedance path to ground.
  • I-type NIB should not see a high impedance.
  • Various sets of heuristics are used when NIB paths are not clearly inductive or capacitive in nature. During I-type checking, any impedance higher than 1 e3 Ohms is considered an open circuit, while during V-type verification, any impedance lower than 0.1 Ohms is considered a short-circuit. See SSN flag option to modify these values.

The recommendation produced when this option is enabled should be followed unless it causes simulation accuracy to decrease. In the latter case, the user should contact Opal-RT support.

Use LDLT nodal admittance matrix factorization(new in ARTEMiS 7.2.0): the SSN solver now offers a new, faster LDLT factorization for the admittance matrix factorization. Setting this option ON will force SSN to use this new factorization. In some cases, LU factorization may be required, in the case where the global admittance matrix is not symmetric. SSN Synchronous machines, DFIM and PMSM can produce unsymmetrical admittance matrices if their speed term is included directly in the state matrix (as opposed to delayed injection).

Advanced Tab

Extinction angle computation (individual thyristor only): this option makes ARTEMiS compute the extinction angle of the thyristors of the model. The computed extinction angle is outputted at the 1 output of individual SPS thyristors (see figure below).

This output angle is a number between 0 and 1 representing the time elaspsed between the previous time step hit and the actual zero-crossing of current that caused the thyristor to open. The option is also available with the SSN algorithm. See demos artemis_ITVC_ExtinctionZeroCrossing.mdl and artemis_ITVC_ExtinctionZeroCrossingSSN.mdl for more explanations.

Use ARTEMiS transformer saturation method: this option makes ARTEMiS uses a flux state for the magnetization inductance and saturation of the transformers.

Distributed Parameter Line model type: this option allows the user to swap between ARTEMiS DPL model or SPS DPL model. Only the latter one can be used for load flow calculations. The ARTEMiS Distributed Parameter Line models are required to enable the parallel simulation of subnetworks separated by them in the RT-LAB framework.





Other Notes

Number of switches in ARTEMiS state-space solvers and SSN

The SSN method main purpose is to uplift the limitation on the number of switches that a model can contain in state-space approach. There is always a SSN group separation method that will allow full pre-calculation of all matrices and real-time simulation. Switches can even be alone in a group by themselves like in EMTP.

With the ARTEMiS-SSN solver, the switch limitation of old ARTEMiS state-space solvers is waived but the user must create groups with a limited number of switches to limit memory usage by the stored matrix permutation inside the groups. Consequently, switch number should be limited to reasonable number in each group(12 and lower for example per SSN group).

At the limit of SSN, one can mimic the classic EMTP approach and use only one switch and nothing else in a SSN group. This is perfectly valid in SSN but would produce huge nodal admittance matrix and may be not efficient in real-time when there are many switches.

Interpolation Methods

ARTEMiS v6 and later automatically incorporates many interpolation methods that were previously manually enabled.

There are 3 types of interpolations implemented in ARTEMiS:

Impulse Event DetectionThis type of interpolation occurs when a forced switch action instantaneously induces a limit condition on another natural switch like a diode. A good example of this is in buck converter where the opening of a IGBT instantaneously put the free wheeling diode in conduction. This type of event is now supported by default in ARTEMiS v6 and later.
Inlined Thyristor Valves Compensation (ITVC, ITVC-SSN)This algorithm corrects the firing jitter of thyristor valves caused by fixed step sampling of the gate signals. It automatically activates if the gate signal is a double number ranging continuously from 0 to 1. The number (ex: 0.458) indicates the in-step delay since the last sample time. The method deactivates if the number is the usual binary number used to control switches. The method is implemented in both state-space and SSN algorithms. It is used with standard Thyristor block of SPS.
Inlined Voltage Inverter Compensation (IVIC-SSN)Available in SSN only, the IVIC-SSN method will compensate the simulation of voltage inverter modeled with SPS Universal Bridge blocks in a way similar to RTeDrive TSB blocks. It automatically activates if the gate signal is a double number ranging continuously from 0 to 1. The number indicates the in-step delay since the last sample time. The method naturally accounts for all working modes of the inverter, including high impedance case. The IVIC method can only be used with a special inverter model available in the SSN library.
Other types of interpolationCustom interpolation methods are proposed in some SSN demos. See the demo ThreeLevelInverter_IVIC_RTE2.mdl for example of a 3-level NPC inverter model.

Iterative Methods

ARTEMiS v7 and later supports real-time iteration for switches and surge arresters. the method is usable with standard SPS switch blocks. Iterative surge arresters (MOV) requires a special MOV block available in the SSN library.

SSN solver used for all submodels.

ARTEMiS v7.3 and later use the SSN S-function even for parts of the model that are not modeled with SSN using NIBs. Such state-space models are considered special cases of the SSN solver but with only 1 group.

Direct FeedthroughN/A
Discrete Sample TimeYes
RT-LAB XHP supportYes
Work OfflineYes

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