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Description

The ARTEMiS Stubline block implements an N-phase distributed parameters transmission line model with exactly one-time step propagation delay and is optimized for real-time simulation.

The ARTEMiS Stubline block permits the decoupling of state-space system equations of networks on both sides of the stubline.

The ARTEMiS Stubline block implements an N-phase distributed parameters transmission line model with exactly one-time step propagation delay. The model is based on Bergeron's travelling wave method used by the Electromagnetic Transient Program (EMTP). This block is similar to the SPS distributed parameters line block but is optimized for discrete real-time simulation and allows network decoupling. It also allows multi-CPU simulation on an RT-LAB simulator.

Refer to the SPS Distributed Parameter Line block Reference page for more details on the mathematical model of the distributed parameters line.

Network Decoupling

One of the main advantages of the ARTEMiS line blocks (Distributed parameters lines and Stublines), by opposition to the SPS lines, is the decoupling of the electric circuit into smaller subnetworks. This important property allows ARTEMiS to simulate, in real-time, a circuit with more switching elements.

SPS and ARTEMiS solve electric circuits using the common state-space method. One of the main limitations of this method is related to the switch elements. When an event occurs that changes the topology of the circuit (or change the state of a switch), SPS and ARTEMiS need to compute a new state-space matrix. This calculation causes a non-acceptable overhead when simulating a circuit in real-time.

To solve this problem, ARTEMiS stores the state-space matrices of a given set of topologies, normally the steady-state topologies, in cached memory and uses them when necessary without having to recalculate the matrices. However, the number of matrices required to cover all topologies of the system depends on the number of switch elements. When a circuit contains a lot of switch elements, the number of required topologies is high and it is not possible to store all matrices in cached memory because of the size of the matrices.

The decoupling property of the line allows ARTEMiS to divide the state-space system in two different state-space systems and reduce the total size of the state-space matrices in memory. It also reduces the maximum number of topologies by an important factor.

RT-LAB Simulation Using a Cluster of PCs

The distributed configuration of RT-LAB allows for complex models to be distributed over a cluster of PCs running in parallel. The target nodes in the cluster communicate between each other with low latency protocols such as shared memory, FireWire, SignalWire or InfiniBand, fast enough to provide reliable communication for real-time applications.

However, electrical circuit cannot be easily distributed over a cluster of PCs without changing the dynamic behaviors of the system. The communication delays degrade the computation.

ARTEMiS lines (Distributed Parameters Lines and Stublines) can be used to distribute a circuit over a cluster of PCs. ARTEMiS used the intrinsic delay of the line to split the circuit without affecting the dynamic property of the system. Moreover, SPS and ARTEMiS use physical modelling lines and connectors to model the circuit.

This type of signals cannot be used by RT-LAB to communicate signals between subsystems, because the RT-LAB opcomm block only supports basic Simulink signals.

The only exception to this rule is the ARTEMiS Distributed Parameters Line block and the ARTEMiS Stubline block. RT-LAB allows the insertion of a line block at the root level of the block diagram and the connection of the physical modelling ports of the block to the real-time subsystems. Also, note that the physical modelling signals and ports do not have to pass through the OpComm block.

Table of Contents

Mask and Parameters


Number of phases NSpecifies the number of phases, N, of the model. The block dynamically changes according to the number of phases that you specify. When you apply the parameters or close the dialog box, the number of inputs and outputs is updated. Available numbers are 1 to 6 and ’2 (differential input)’. The differential input option is useful when using ARTEMiS Stubline in case where it does not have to be referred to the ground as in stubline transformer applications.
Per-Unit value specificationSpecify if the resistance and inductance value are specified in per-unit or not.
Resistance (Ohms)
The total resistance  in ohms or pu.
Inductance (H)
The total inductance, in Henry (H) or pu.
Nominal power (VA)Nominal power base (for per-unit values only).
Nominal voltage(V)Nominal voltage base (for per-unit values only).
Nominal frequency (Hz)Nominal frequency base (for per-unit values only).
Sample TimeThe block sample time, in seconds.


Inputs and Outputs

Inputs

N-Phases voltage-current physical domain connection.

Outputs

N-Phases delayed voltage-current physical domain connection.

Characteristics and Limitations

The ARTEMiS Stubline block does not initialize in steady-state so unexpected transients at the beginning of the simulation may occur.

Direct FeedthroughNo
Discrete Sample TimeYes
XHP SupportYes
Work OfflineYes

Example

This section provides an example on how to build a 3-phase stubline transformer. The stubline transformer will exhibit a decoupling delay between the primary and secondary sides suitable for distributed simulation real-time simulation of large systems. Such a transformer could be used to decouple HVDC system equations at the rectifier/inverter station transformers and compute each equations in parallel on different CPUs or cores. The model is part of the ARTEMiS demos and is named artemis_Transfo_Stubline (.mdl).

In the example, we construct a stubline-based 3-phase transformer from an original SimPowerSystems transformer and compare the no-load and short-circuit responses. The principle used to build the stubline transformer is to ’move’ the secondary windings leakage inductance and resistance in stublines put in series with the windings themself. This is done using single-phase transformers first, then adjusting the per-unit stubline parameters and finally to make the Y ou Delta connections after the stubline.

The example uses a SPS 3-phase transformer with the following parameters:

We will build the stubline 3-phase transformer using single-phase transformer using pu values. Since we will also use pu-based differential stubline (a stubline with no built-in ground referentials), appropriate single-phase per-unit bases have to be found. First, the total 3-phase nominal power has to be divided by 3 when configuring single-phase transformer inside. Secondly, the 3-phase winding voltage takes into account the connection type (Y or Delta) in the voltage specification while single-phase transformer has no such thing. Third, the R-L pu specification of a 3-phase transformer are specified as ’Y-connection equivalent values’.

In the final, the resulting single phase transformer therefore has the following parameters:



Note: The single-phase transformer winding that are Y connected have their voltage ratio divided by a sqrt(3) factor. Also note the single phase nominal power is 1/3 of the nominal 3 phase power typically used in 3-phase transformer specifications.



The ARTEMiS Stubline put in the Y connection has the following parameters:

While the ARTEMiS Stubline put in the Delta connection has the following parameters:



Note: The bases used are consequent with the parameters of the single-phase transformer. The R-L per-unit values are the same than in the 3-phase transformer (because 3-phase transformer impedance in Per-Unit is typically specified for the Y equivalent. Only the base voltage values differ depending on the connection type.



The design of such transformers is often tricky because of the possible errors in the base conversion. It is always advisable to compare the stubline model with a reference for no-load and short-circuit cases to verify the correctness of the design. This is what is done in the example where we superpose the voltages and currents of the stubline transformer with a standard SPS model.

Finally, this model can be simulated in several CPU if the model is separated in accordance to RT-LAB rules with the stublines used as inter-CPU decoupling elements placed on the top-level of the Simulink model.

See the artemis_Transfo_StublineRT.mdl demo for details on how to use the stublines to decouple and simulate such a model on several cores/CPUs in RT-LAB.

Limitations

Usage in RT-LAB as task decoupling elements

When used in RT-LAB to decouple and separate computational tasks on different cores/CPUs, the following connection restriction are applicable to the ARTEMiS Stubline model:

  • The ARTEMiS Stubline must be located on the top-level of the RT-LAB compatible Simulink model (as in Figure 9 for example)
  • Each ARTEMiS Stubline outports can be connected only to SimPowerSystems component located inside RT-LAB top-level subsystem (names beginning with ’SS’ or ’SM’ prefixes)
  • No connection between stublines is allowed on the top-level. If such a connection is required (ex: star-connection neutral point), the ARTEMiS Stubline lines must be first routed inside the subsystems individually and the connection between the ARTEMiS Stubline ports can be made inside the subsystem.



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