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# Description

The TSB 2-Level block implements a 2-level IGBT/GTO/MOSFET inverter with 2 active switches with anti-parallel diodes. The block model uses a switching function approach with interpolation and is also capable of simulating cases where the inverter output is in a high-impedance state (ex: no gating or natural rectification). Deadtime and anti-parallel diode effects are fully taken into account by this model. The gates are controlled by Double signals. The following figure presents the equivalent electrical circuit of the TSB 2-Level block.

A numerical RC snubber is required to implement high impedance states when no gating is present at both switches. Suggested values are given next:

$$\mathrm{R}_{\mathrm{Snubber}}=\frac{\pi}{\mathrm{Ts} \cdot 5} \cdot \mathrm{L}_{\mathrm{eq}}$$ $$\mathrm{C}_{\mathrm{Snubber}}=\frac{1}{\left(\mathrm{L}_{\mathrm{eq}} \cdot \frac{2 \cdot \pi}{\mathrm{T} \mathrm{s} \cdot 15}\right)^{2}}$$

Where Leq is the minimum equivalent inductance of the load (connected to ’A’ port) and Ts the simulation time step.

The Input DC current is normally equal to the current goiing across the upper IGBT. An alternative method is also provided based on power balance (Idc*Vdc=Vabc*Iabc). A compensation factor is provided to adjust this power equation. This factor simply makes the interpolation across the two last values of Iabc to compute Idc. This can be required in applications with very low power factors such as an inductive machine with very low mechanical load.

# Block

Switch Conduction resistance [Ohms] Conduction resistance of all switches, including anti-parallel diodes. Snubber resistance value, only used in high impedance mode. Snubber capacitor value, only used in high impedance mode. Time at which the capacitor voltage will be computed. This is the equivalent resistance of the inverter at voltage reversal on the DC-bus. This resistance is different in this model than the conduction resistance of the two anti-parallel diodes, diodes that would start to conduct in case of DC-bus voltage reversal, because of the switching function method of the model. With this option selected, the DC bus input current is computed from the power balance equation (Vdc*Idc=Vabc*Iabc). This factor enables some delay tuning in the power equation Vdc*Idc=Vabc*Iabc by interpolating on the 2 last time value of Iabc. It can be useful in low power factor applications.

# Inputs and Outputs

## Inputs

Gate (double, interpolated) (vector of size 2). Double signals that controlled the upper and lower switch gates. A signal value of 1 indicates the switch is conducting, while a value of zero indicates the switch is OFF. A values between 0 and 1 indicates that a switching action occurred during the last time step. The positive and negative side of the DC bus. The inverter middle point.

None.

# Limitations

The normal operation of TSB is with non-null load current and active pulsing. IGBT dead time is handled correctly in this mode. Other operational modes require more caution.

High-impedance mode When the 2 IGBT gates are OFF and the current goes to 0, the TSB enters in so-called ’high-impedance mode’ for which internal RC-snubber is activated (See Description).Numerical instability can occur if the RC-snubber is not adjusted correctly. This mode is not supported by the TSB. This type of fault is major and could easily destroy a real inverter. It should be avoided anyhow. One way to detect this type of fault in HIL testing is to verify at the TSDIN in the model if the condition occurs. This can be done by taking the TSDIN output pair into a single RT-Events AND block and after into an RT-Events Converter to ’double with interpolation’. A result greater than 0 from RT-Events Converter will indicate a DC short-circuit fault.

# Characteristics

Direct Feedthrough No Parameter Yes Yes

# Related Items

Since ARTEMiS 7.3.2, new TSB models are available in the SSN section of ARTEMiS. These so-called TSB-RD notably have easier and more stable snubber adjustments.

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