Real-time step size per core for typical models
The following figure shows how many states can be simulated per core. All models were simulated using only one core per RT-LAB subsystems (SM_ SS_).
LU and LDLt factorization performance on model with large admittance matrices
The Nine-level motor drive with multi-winding zig-zag feeding transformer(SSN) demo has 39 SSN nodes mainly used to compute the 3*4=12 diode rectifiers (72 switches)
A similar model with 17-level inverter with multi-winding zig-zag feeding transformer was designed for a client (confidential) in which there are 76 SSN nodes and a total of 3*8=24 diode rectifiers (144 switches)
In these models, the factorization part of the SSN algorithm is dominant by factors of 1.5 (39 nodes) and 3 (76 nodes) and we compare the calculation time of both LU and LDLt factorization methods below.
Calculation time on Opal-RT OP4510 in micro-seconds. (3 cores max available)
39 node model, 72 switches, 2 core available for the rectifiers:
- 1 core : LDLT:31.2 LU 42.8
- 2 core : LDLT:26.3 LU 38.0
76 node model, 144 switches, 3 cores available for the rectifiers:
- 1 core : LDLT:133.4 LU 205.9
- 2 core : LDLT:125.6 LU 195.5
- 3 core : LDLT:114.5 LU 183.3
Parallel SSN efficiency on the bipolar HVDC demo
This section provides some SSN parallelization performance benchmark on the Bipolar 12-pulse HVDC link with switched filter banks and Firing Pulse compensation demo.
The HVDC inverter and rectifier stations have 19 SSN nodes each and 44 and 49 switches respectively. In this model, the state-space operation count is approximately 4 times higher than the LU/LDLT factorization operation count.
The following measurements were taken with the LU factorization. LDLt factorization should further improve performance.
Calculation time on Opal-RT OP5700 in micro-seconds. (12 core max available, worst subsystem performance displayed)
- 1 core each for both inverter and rectifier: LU 50.9
- 2 cores each for both inverter and rectifier: LU 43.6
- 3 cores each for both inverter and rectifier: LU 41.5
* Above 3 cores each, performance does not improve.*