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The circuit shows the capability of ARTEMiS-SSN to accurately simulate current source inverters.

This model is composed of back-to-back current source inverters connected with a cable with self and mutual inductance.

Because the cable has a mutual inductance, using stublines to decouple the two inverters cannot be used. Additionally, note that the IGBT used in this configuration DOES NOT have anti-parallel diodes.

Demonstration

SSN was therefore used to decouple the two inverters successfully, resulting in a model with 2 SSN groups of 6 switches (IGBT/diode). The user can, therefore, add fault emulating switches to this model for advanced control testing.

The user can check the accuracy of the SSN model by comparing it to SPS counterpart. This can be done by simply deleting the ARTEMiS GUIde block from the model; the SSN Nodal Interface Blocks (NIB), with I- V-ports, become inactive then.



Note: This demo is NOT compensated for switching events occurring in the middle of time steps (as opposed to the "ARTEMiS-SSN Inlined Time-Stamped Bridge in 2-level VSC-based HVDC applications" demo) but the accuracy is still very good.

This demo is executable in RT-LAB as it's already separated into SM_ and SM_ top-level subsystems.


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