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The circuit shows the capability of ARTEMiS-SSN to simulate a large thyristor-based bipolar 12-pulse HVDC link with switched filter banks.

The model also has the following features:

  • SSN Inlined Thyristor Valve Compensation (ITVC) to improve accuracy. The firing pulse unit is made with RT-EVENTS but can directly accept thyristor gate pulses from I/Os of the simulator. ITVC minimizes the current jitter amplitude on the DC bus.
  • Seven switched filter banks
  • Two 12-pulse thyristor converters on each station, 1 per pole.

The complete model has a total of 42 switches and 19 SSN nodes on each station, for a grand total of 84 switches (there is no limit on the switch number in SSN). The complete system can be simulated at a time step of 48 µs on RT-LAB running on a server-class Xeon PC.

To achieve this performance, the SSN parallelization feature is used in which the different SSN group equations are simulated in parallel WITHOUT any delays.

  Fig.1 Bipolar HVDC-link with switched filters

Demonstration

During the simulation of the model, the following things happen:

  • The HVDC current is increased to the nominal values
  • Capacitive filter banks are switched ON one by one and this has the effect of slightly increasing the rectifier AC voltage and consequently increasing the firing angle to maintain the same DC current.

By default, the firing compensation is turned ON. If you want to observe the 'effect' of non-compensation, go into the Console subsystem and set 'Not_compensated(if==1)' equal to 1.

  Fig.2 Effect of ITVC algorithm on DC-link current

References

[1] C. Dufour, L.-A. Grégoire, J. Bélanger, "Solvers for Real-Time Simulation of Bipolar Thyristor-Based HVDC and 180-cell HVDC Modular Multilevel Converter for System Interconnection and Distributed Energy Integration", 2011, CIGRÉ conference proceedings, Recife, Brazil, April 3-8, 2011.

[2] C. Dufour, J. Mahseredjian, J. Bélanger, J. L. Naredo, "An Advanced Real-Time Electro-Magnetic Simulator for Power Systems with a Simultaneous State-Space Nodal Solver", IEEE/PES T&D 2010 - Latin America, São Paulo, Brazil, Nov. 8-10, 2010


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