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This example shows how to simulate a power system with an MMC-HVDC link, all simulated on CPUs with controllers inside the model.

The number of cell per arms is moderate in this demo (=40). For cases with much higher cell counts, up to 512 per arm, it is recommended to model the MMC inverters on FPGA. See [1] for further details.

Note: This demo requires Opal-RT MMC blockset to be installed.

  Figure 1: Typical MMC link (parameters shown are not the one of this demo)

Running the demo

  • When the system starts pre-charge, at that time all of the breakers (include dc and ac breakers) are opened, both pulses are off, the capacitors are precharged, and the dc voltage for the left terminal should be charged to around 0.6 p.u.
  • Once the pre-charging of the capacitors is finished, close the left terminal ac breaker, both pulses are off, the dc voltage for the left terminal is charged to around 0.7 p.u.
  • Enable the pulse of the left terminal, the dc voltage for the left terminal is 1 p.u.
  • Set the reference value of the reactive power of the left terminal, the real Q value should be the same as the reference Q value.
  • All of the above steps are the same for the right terminal.
  • After finishing the above steps for both left and right terminals, close the dc breaker and see the dc voltages on both sides, set the reference value of the real power P, the real value of P should track the reference value.


[1] C. Dufour, W. Li, X. Xiao, J.-N. Paquin, J. Belanger, “Fault studies of MMC-HVDC links using FPGA and CPU on a real-time simulator with iteration capability”, 11th International Conference on Compatibility, Power Electronics and Power Engineering (IEEE CPE-POWERENG 2017), Cadiz, Spain, April 4-6, 2017.


The same model is available in beta version using SSN User Custom Blocks for the MMC arms. The model uses the fully nodal model for the rectifier side of the MMC link. Notably, the DC voltages are more realistic in natural rectification mode.

Open the model with SSN-UCB

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