Pour la documentation en FRANÇAIS, utilisez l’outil de traduction de votre navigateur Chrome, Edge ou Safari. Voir un exemple.

The circuit shows the capability of ARTEMiS-SSN to simulate thyristor extinction angles.

ARTEMiS comes with the ITVC (Inlined Thyristor Valve Compensation) algorithm which enables it to compensate for the firing delays of thyristors in a fixed time step simulation. (This option is always included in the simulation, hence the term Inlined).

When the user checks the Extinction angle computation (individual thyristor only) of ARTEMiS, the first output of SPS individual thyristor measurements is replaced by the thyristor extinction angle.

In many thyristor-based HVDC systems, it is important to obtain a precise extinction angle measurement to avoid thyristor misfiring. One problem is that this turn-off time can occur in the middle of time steps during a real-time simulation. The ARTEMiS-SSN algorithm provides an accurate thyristor turn-off time by providing a timestamp of the actual turn-off time during the time steps.


This model implements a 6-pulse thyristor converter in which the thyristor extinction times are computed using timestamps.

The output timestamps have the following meaning: whenever the timestamps value x is greater than 0, it means that the thyristor has turned off during the last time step at x/Ts seconds after the last simulation time step (Ts is the simulation time step).

In the model, with the ARTEMiS option 'Extinction angle computation angle (individual thyristor only)' turned ON, the thyristor outputs the extinction angle instead of the thyristor current. Thyristor voltage is still outputted normally.

To observe correctly this feature, one must look at the extinction angles in steady-state (Pink scope named 'extinction'). The pulse has a regular sequence despite that the sample time of the model (40µs) is not a multiple of the firing pulse frequency.

The model also includes some conversion blocks to interface this feature with Time-Stamped Digital Output in an RT-LAB application. (Note that the RT-LAB I/O blocks in this model are only for demonstration purposes here because the model is not separated for RT-LAB compilation.)

  • No labels