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Description

The OPAL-RT board I/O interface allows the user to configure the various OPAL-RT analog and digital I/O boards.

To access the user interface, click on the I/O Interface Configuration button in the HYPERSIM ribbon options; in the window that appears, right-click on the OPAL-RT Board item and select Add. After giving a relevant name to the I/O interface, its user interface will be available for use.

The I/O interface must be configured and valid connections must be defined before the I/O interface can be initialized at simulation start.

One  I/O interface per FPGA must be used. In order to differentiate them, they must have different names.

Bitstream Configuration

Every bitstream file (.bin) programmed into an FPGA to be interfaced with the  I/O interface must have a bitstream configuration file associated to it. This is because the I/O interface requires a description of the hardware installed in the simulator to correctly interface with it.

A bitstream configuration file describes the functionalities of its associated programmable file.

The configuration contains information about I/O communication and the presence and configurability of other logic blocks (such as electric solvers) in the RT-XSG model used to generate the programmable file.

Before loading the I/O interface with a specific configuration, the user must ensure that the bitstream file (.bin) described in the associated configuration file (.opal) has been programmed.

Associating a configuration to its corresponding programmable file is easy, since their names should appear the same, as in this example: the configuration is called "TE0741_3-EX-0001-3_2_3_354-16Aio_32sDio_6PWMExpansionSlot_HSL_Example_Model-12-07.opal". In this case, the bitstream file should be named: TE0741_3-EX-0001-3_2_3_354-16Aio_32sDio_6PWMExpansionSlot_HSL_Example_Model-12-07.bin

For a list of the possible chassis and board/module combinations, consult the List of Compatibilities section.

See the General Configuration section below for more details on changing and loading bitstream configurations.

Configuring Remote I/Os

Loading the bitstream configuration will let users know if the MuSE (Multi-System Expansion link) feature is supported. This feature expands the I/O capability of the simulator by enabling the connection to multiple FPGA-based I/O expansion chassis or OP4200 systems. Thus, it allows the user to configure, connect to and control I/Os that belong to a remote FPGA. The connection is done through high-speed optical fiber cables and SFP transceivers, using the SFP sockets available at the front or the left side of the chassis.

The user can verify if the MuSE feature is supported directly after loading a bitstream configuration file. If the feature is present, a list labeled Remote Board Configuration will appear in the UI. From then on, the system can be referred to as a central system. A central system is an FPGA whose bitstream gives it the capability of connecting to one or multiple remote FPGAs.

One remote chassis can be connected to each SFP socket of the central. The network of central and remote chassis is thus a star topology, with the central system in the center and the remotes as its endpoints.

The remote chassis being endpoints cannot in-turn be used as central systems (daisy-chaining of remotes is not supported), so a bitstream file prepared for a remote chassis cannot be used for a central system.

Hardware synchronization of the systems is achieved through the same high-speed link as the one used for data transfer (i.e. only one cable is required at all times between the central system and any of its remotes).

Unlike the PCIe expansion chassis, the order in which the systems are powered on, or the order in which the cables are connected, does not matter. Nor does it matter whether or not the systems are on while the cables are being connected.

What is important is that the system topology is set in place (i.e. all cables connected according to the simulation's requirements) before the start of the simulation, and remain connected throughout the simulation.

Changes to the topology cannot be made while the simulation is running.

The programming of remote bitstreams is to be done by invoking the flashing application executed on the central system. For more information on how to do this, please contact OPAL-RT's support team.

Please check the Remote Board Configuration section below for more information on how to set up remote systems.

Restrictions to using the Multi-System Expansion link with  software architecture may apply depending on your application and software configuration. To verify compatibility, please contact OPAL-RT's support team.

For a list of the possible chassis and board/module combinations, please consult the List of Module Compatibilities for the MuSE feature section.

Interface Overview: Configuration

The I/O interface is entirely configurable via the HYPERSIM GUI. The parameters available for configuration are presented in this section.

General Configuration

The following options can be configured when clicking on the I/O interface main configuration page:

Chassis type

Select the FPGA board type to be used in the simulation.

Chassis IDEnter the chassis ID of the selected FPGA board to be used in the simulation.
Clock modeChoice between HW (hardware) or SW (software). The choice of clock establishes if the FPGA will drive the simulation (hardware mode) or the CPU (software mode).
Use external synchronization sourceIf selected, the board uses an external hardware synchronization source as opposed to its internal clock. This option is not taken into account if the Clock mode is SW.
Type of generated synchronization signal

If the Use external synchronization source box above is un-checked, then this parameter will be visible, allowing the user to choose the medium where the FPGA will output its synchronization pulse: choices are through the optical cable or through the audio cable.

This parameter is only relevant when Clock mode is HW.

Operate as hardware synchronization source

This checkbox is only visible if the Use external synchronization source checkbox above is enabled. Its purpose is the following:

  • When enabled, the FPGA will be configured to use the external synchronization source received to synchronize the simulation (master-with-external-clock mode)
  • When disabled, the FPGA will be configured to use the external synchronization source received but it will not qualify to drive the simulation (slave mode)

This parameter is only relevant when Clock mode is HW.

Type of expected synchronization signal

This parameter is only visible if the Use external synchronization source checkbox above is enabled. It is a drop-down menu giving the user the choice to synchronize either through copper or optical cables.

This parameter is only relevant when Clock mode is HW.

Bitstream configuration file path

A file-browsing field.

  • Clicking on it opens a File Explorer window, allowing the user to navigate to the bitstream configuration file.
  • This file must be in the [board_type]_[file_name].opal format. Example: VC707_2_Config1.opal.
  • The use of a bitstream configuration file implies that the user has also built the bitstream (.bin file) (following the naming convention mentioned above) with RT-XSG. For more information, please contact OPAL-RT's support team.
  • Once selected, the I/O configuration contained in the file appears immediately: the Folders section of the I/O interface configuration panel updates to show the I/O capability of each slot as described in the file.
Show advanced configuration

If selected, the options presented below will be made available to the user.

Note: these options require advanced knowledge of the I/O interface capabilities

Time step factor

Denotes a multiplier for the board's speed in relation with the model's timestep.

Only visible when Show advanced configuration checkbox is enabled.

Level of logging

Select how verbose the log should be. The higher the level, the more impact it can have on simulation performance.

Only visible when Show advanced configuration checkbox is enabled.

Enable the firmware generated update request signal

This feature is only available in SW synchronized mode and when the sending of data is done at the beginning of the calculation step. When enabled, it allows the firmware to generate the update request signal instead of letting the software application generate it.

Only visible when Show advanced configuration checkbox is enabled.

Disable strict hardware mismatch validationIf selected, the use of multiple I/O card types based on general compatibility rules will be activated instead of exact hardware ID values.

Slot configuration

When clicking on this section, the fields provide the following information to the user:

NameThe name of the slot; it describes the location in the simulator chassis and its functionality
DescriptionElectrical characteristics of the board defined in this slot
FunctionalityI/O type and direction of the board defined in the slot
I/O card typeI/O board identifier. In the case of OP4200, this represents the cassette's identifier.

Other parameters may appear here, depending on the I/O board type.

Channel Group Configuration

A group contains 8 channels, with the following configurable options:

  • Enable: Enables data transmission/reception of the specified channel group.

Other parameters may appear here, depending on the I/O board type.

Signal Configuration

This section allows the user to configure the characteristics (if any) of each of the 8 channels available in a group. The content of this panel varies based on the I/O board type defined in the slot.

For more information regarding the detailed configuration of the signals, refer to the corresponding I/O type documentation in the sections below:

Remote Board Configuration

Adding remote systems to the configuration is done by clicking the Insert button in the Remote Board Configuration list. This list is only visible if the MuSE feature is available in the current bitstream configuration. 

The name of each remote can be easily changed in the remote list view of the UI. Following this, the configuration of each remote (such as chassis type, chassis ID, bitstream configuration and so on) is done by clicking on the respective remote in the UI. The view that appears is the same as the one for the central system. Users can refer to the beginning of the current section, starting with General Configuration for more information.

Similarly to central systems, bitstream configuration files describing bitstreams for central (or standard, non-MuSE) FPGAs cannot be loaded for remote systems.

When the remote system chosen is an OP4200, the user has to provide its MAC address. The MAC address can be found by running the "ifconfig" command on the remote system, or by consulting the delivery binder. The format expected is XX:XX:XX:XX:XX:XX, where 'X' is a hexadecimal digit (0-9, A-F).

Currently, remote systems are forced to be synchronization slaves. This can be seen through the Use external synchronization source checkbox being selected but grayed out. Remote systems must be synchronized with the central system (i.e., they cannot use any other synchronization source). The physical synchronization between central and remote systems is done through the same optical cable used for the data transfer (i.e. only one cable is needed between a central and any remote).

Connections

Once the I/O interface has been configured, the user must connect points in the model to points in the I/O interface. This can be done using the standard HYPERSIM workflow for connections.

The I/O interface connectable points depend on its configuration, namely on the available types of I/Os and number of channels enabled for each I/O board.

To get a list of the possible connectable points of each I/O type, refer to its specific documentation. The available I/O types are listed in the following section.

Supported I/O Types

I/O NameDirection
Analog InTo model
Analog OutFrom model
Digital In To model
Digital OutFrom model
Raw Data from BoardTo model
Raw Data to BoardFrom model
Asynchronous Raw Data From Board (Load OUT)To model
Asynchronous Raw Data To Board (Load IN)From model

Limitations

The current version of the  I/O interface has the following limitations:

  • The "Disable strict hardware mismatch validation" feature is not available on OP5142 (OP5600).
  • On all chassis, FPGA-simulated motor models are not supported at the moment.

List of Compatibilities

Chassis and FPGA board

Supported

OP4200 with a MEZX5 moduleNo
OP4500 with a MMPK7 moduleNo (platform deprecated)
OP4510 with a TE0741 module Yes
OP4520 I/O expansion box with a TE0741 module Yes
OP5600 with an OP5142 board No
OP5600 with a ML605 board No (platform deprecated)
OP5650 with an OP5143 boardYes
OP5607 I/O expansion box with a VC707 boardYes
OP5707 with a VC707 boardYes
OP7020 I/O expansion box with a VC707 boardYes
OP7160/OP7161No (platform deprecated)
OP7170Yes

Limitations of the Multi-System Expansion Link Feature

Restrictions to using the MuSE link with the  software architecture may apply depending on your application and software configuration. To verify compatibility, please contact OPAL-RT's support team.


List of Module Compatibilities for the MuSE feature

Chassis and FPGA board 

Central 

Remote

OP4200 with a MEZX5 moduleNoYes
OP4500 with a MMPK7 module NoNo
OP4510 with a TE0741 module YesYes
OP4520 I/O expansion box with a TE0741 module Yes, if connected via PCIe to a simulatorYes
OP5600 with an OP5142 board Yes
No
OP5600 with a ML605 boardNoNo
OP5607 I/O expansion box with a VC707 board Yes, if connected via PCIe to a simulatorYes
OP5700 with a VC707 board YesYes
OP7020 I/O expansion box with a VC707 boardYes, if connected via PCIe to a simulatorYes
OP7160/OP7161NoNo
OP7170YesYes


General Compatibility Rules for Multiple I/O Card Types

I/O cardTypeDescriptionCompatible with
OP5340AINOPAL-RT OP5340 SCMB, 16 ch, 16 bit, 1us, A/D, +-5 V to +- 100VOP5340; OP5340-2; 
OP5340-2AINOPAL-RT OP5340-2 SCMB, 8 ch, 16 bit, 1us, A/D, +-5 V to +- 100VOP5340; OP5340-2; 
OP5330-1AOUTOPAL-RT OP5330-1 SCMB, D/A 16 Ch@35ma Digital to Analog Module

OP5330-1; OP5330-3;

OP5330-3AOUTOPAL-RT OP5330-3 SCMB, D/A 16 Ch@15ma Digital to Analog Module'OP5330-1; OP5330-3; 
OP5351DINOPAL-RT OP5351 TTL Digital Mezzanine - 32 DinOP5351; OP5353; OP5357; OP5358-3; OP5358-5; 
OP5353DINOPAL-RT OP5353 Opto-Isolated Digital Mezzanine - 32 DinOP5351; OP5353; OP5357; OP5358-3; OP5358-5; 
OP5357DINOPAL-RT OP5357 LVDS Digital Mezzanine - 32 DinOP5351; OP5353; OP5357; OP5358-3; OP5358-5; 
OP5358-3DINOPAL-RT OP5358-3 Digital Mezzanine 3V RS422- 32 DinOP5351; OP5353; OP5357; OP5358-3; OP5358-5; 
OP5358-5DINOPAL-RT OP5358-5 Digital Mezzanine 5V RS422 - 32 DinOP5351; OP5353; OP5357; OP5358-3; OP5358-5; 
OP5352DOUTOPAL-RT OP5352 TTL Digital Mezzanine - 32 DoutOP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; 
OP5354DOUTOPAL-RT OP5354 Opto-Isolated Digital Mezzanine - 32 Dout

OP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2;

OP5355DOUTOPAL-RT OP5355 LVDS Digital Mezzanine - 32 DoutOP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; 
OP5356-3DOUTOPAL-RT OP5356-3 Digital Mezzanine 3V RS422- 32 DoutOP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; 
OP5356-5DOUTOPAL-RT OP5356-5 Digital Mezzanine 5V RS422 - 32 DoutOP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; 
OP5359DOUTOPAL-RT OP5359 Open-collector Digital Mezzanine - 32 DoutOP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; 
OP5360-1DOUTOPAL-RT OP5360-1 Digital Mezzanine Push-Pull FET 5 to 15V,  50ns - 32 DoutOP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; 
OP5360-2DOUTOPAL-RT OP5360-2 Digital Mezzanine Push-Pull FET 5 to 30V,  65-200ns - 32 DoutOP5352; OP5354; OP5355; OP5356-3; OP5356-5; OP5359; OP5360-1; OP5360-2; 
OP5363DINOPAL-RT OP5363 High Impedance Dual Threshold - 32 DinNone


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