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Power Electronics Add-On Configuration Page

In the System Explorer window configuration tree, expand Targets >> Controller >> Custom Devices and select Power Electronics Add-On to display this page.  If this is a new VeriStand project, see the instructions in How to Add the Power Electronics Add-On to the System Definition.

This page includes the following components, configurable at edit-time only:

Ribbon Buttons

Launch HCM

Launches the Hardware Configuration Manager. The Hardware Configuration Manager (HCM) is a tool used to create, edit, and remove Hardware Configurations
Power Electronics Add-On Main Page
VersionSpecifies the version of the Power Electronics Add-On
ConfigurationSelected Hardware Configuration for the project.  The configuration defines the types of FPGA cards to be targeted and the features available in their firmwares.
Configuration DescriptionDescription of the features included in the selected hardware configuration.  For more detailed information about a configuration, navigate to its Help page under Supported Hardware Configurations.
TargetName of the FPGA target onto which the corresponding bitfile will be deployed.  This must match the name of the FPGA target as displayed in the NI Measurement and Automation Explorer.
BitfileFile name of the bitfile to be deployed to the FPGA target.
Target Credentials
Username

Specify the username for the NI Real Time Target.  The default target username is admin. Target credentials can be modified in the NI Measurement and Automation Explorer.

Password

Specify the password for the NI Real Time Target.  The default target password is an empty string. Target credentials can be modified in the NI Measurement and Automation Explorer.

Advanced Performance

Enable Telemetry Channels

Allows telemetry parameters to be exposed as VeriStand Channels. See Telemetry Channels below for more details.

Processor Assignments

Launches the Processor Assignments dialog window.

Power Electronics Add-On Section Channels

The Power Electronics Add-On section includes the following custom device channels. 

Telemetry Channels VeriStand 2019 and 2020

The following channels are available in VeriStand 2019 and 2020 only.  They are displayed under Telemetry Channels when the Enable Telemetry Channels option is enabled in the Power Electronics Add-On configuration page. The channels are grouped according to the process to which they belong. The FPGA Communication Process 1, 2 and Low Latency FPGA Communication Processes are responsible for CPU-FPGA communication (read/write), whereas the Waveform Acquisition Process is responsible for the acquisition of stream data from waveforms.

FPGA Communication Process 1

Channel NameType

Units

Description


Actual Loop Rate

OutputHertzThe execution rate of the FPGA Communication Process.

Iteration

Output
The iteration count of the FPGA Communication Process.

Write Time

OutputusTime taken by the FPGA Communication Process to write the values of the input VeriStand channels to the FPGA model inputs.

Read Time

OutputusTime taken by the FPGA Communication Process to read the outputs of the FPGA models and publish them to the output VeriStand Channels.

Iteration DurationOutputusTime taken to execute the last entire iteration of the process.

Finished Late CountOutput
Number of iterations that have exceeded the specified Loop Rate for this process.
FPGA Communication Process 2

Channel NameType

Units

Description


Actual Loop Rate

OutputHertzThe execution rate of the FPGA Communication Process.

Iteration

Output
The iteration count of the FPGA Communication Process.

Read Time

OutputusTime taken by the FPGA Communication Process to read the outputs of the FPGA models and publish them to the output VeriStand Channels.

Write Time

OutputusTime taken by the FPGA Communication Process to write the values of the input VeriStand channels to the FPGA model inputs.

Iteration DurationOutputusTime taken to execute the last entire iteration of the process.

Finished Late CountOutput
Number of iterations that have exceeded the specified Loop Rate for this process.
Low Latency FPGA Communication Process (One per FPGA Target with Low Latency Support)

Channel NameType

Units

Description


Actual Loop Rate

OutputHertzThe execution rate of the Low Latency FPGA Communication Process.

Iteration

Output
The iteration count of the Low Latency FPGA Communication Process.

Write Time

OutputusTime taken by the Low Latency FPGA Communication Process to write the values of the input VeriStand channels to the FPGA model inputs.

Read Time

OutputusTime taken by the Low Latency FPGA Communication Process to read the outputs of the FPGA models and publish them to the output VeriStand Channels.

Iteration DurationOutputusTime taken to execute the last entire iteration of the process.

Finished Late CountOutput
Number of iterations that have exceeded the specified Loop Rate for this process.

Late SamplesOutput
Number of samples that have been sent late from the Low Latency Process to the Low Latency Engine on the FPGA. This indicates that the CPU has fallen behind.

FPGA System Loop TimeOutputTicks

Measured execution rate of the Low Latency Engine on the FPGA.


CPU Load Time ValueOutputTicksTime measured from the start of the FPGA-to-CPU write data transfer to the completion of the CPU-to-FPGA read data transfer.

CPU Load Time MaximumOutputTicksMaximum CPU Load Time Value.

Transfer Sequence NumberOutput
FPGA-to-CPU Transfer Sequence Number. This value is incremented by the FPGA engine after the FPGA-to-CPU data is transferred to the CPU.

FPGA Communication State

Output
Last reported state of the Low Latency Engine on the FPGA.
Waveform Acquisition Process

Channel NameType

Units

Description


Actual Loop Rate

OutputHertz

The execution rate of the Waveform Acquisition Process.

Iteration

Output
The iteration count of the Waveform Acquisition Process.

Telemetry Channels VeriStand 2018

The following channels are available in VeriStand 2018 only.  They are displayed under Telemetry Channels when the Enable Telemetry Channels option is enabled in the Power Electronics Add-On configuration page. The channels are grouped according to the process to which they belong. The Hardware Interface Process is responsible for CPU-FPGA communication (read/write), whereas the Waveform Acquisition Process is responsible for the acquisition of stream data from waveforms.

Hardware Interface Process

Channel NameType

Units

Description


Actual Loop Rate

OutputHertzThe execution rate of the Hardware Interface Process.

Iteration

Output
The iteration count of the Hardware Interface Process.

Write Time

OutputusTime taken by the Hardware Interface Process to write the values of the input VeriStand channels to the FPGA model inputs.

Read Time

OutputusTime taken by the Hardware Interface Process to read the outputs of the FPGA models and publish them to the output VeriStand Channels.
Waveform Acquisition Process

Channel NameType

Units

Description


Actual Loop Rate

OutputHertz

The execution rate of the Waveform Acquisition Process.

Iteration

Output
The iteration count of the Waveform Acquisition Process.

How to Add the Power Electronics Add-On to the System Definition

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