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Processes Managed by the Power Electronics Add-On Engine

At runtime, both the Power Electronics Add-On Engine and the VeriStand Engine execute their own sets of processes on the Real Time CPU. The processes managed by the Power Electronics Add-On Engine are described in the figure and table below. For more information related to the processes managed by the VeriStand Engine, refer to the VeriStand Engine Help documentation on the National Instruments website.



ProcessDescriptionPriorityDefault Execution Rate
Power Electronics Add-On Inline Process

Highest level inline process in charge of initializing, launching asynchronous processes, shutdown and error handling of the custom device.

High
(Defined by the VeriStand Primary Control Loop)
(Defined by the VeriStand Primary Control Loop)
FPGA Communication Process 1

First asynchronous process establishing read and write communication between VeriStand Channels in Real Time, and their corresponding features on the FPGA. In the case of a hardware configuration with multiple FPGAs, this process communicates with all of them.

High2 kHz
FPGA Communication Process 2

Second asynchronous process establishing read and write communication between VeriStand Channels in Real Time, and their corresponding features on the FPGA. In the case of a hardware configuration with multiple FPGAs, this process communicates with all of them.

High2 kHz
Low Latency FPGA Communication Processes

Set of asynchronous processes for low latency read and write communication between VeriStand Channels and their corresponding features on the FPGA. In the case of a hardware configuration with multiple FPGAs, a process is dedicated to each FPGA.  Low Latency FPGA Communication is available in VeriStand 2019 and up.

High10 kHz
Waveform Acquisition Process

Asynchronous process in charge of data communication between the FPGA target and VeriStand Waveforms on the Real Time CPU.

Low100 Hz

Processor Assignments Dialog Window

The Processor Assignments Dialog Window is used to assign specific CPU processors to the Power Electronics Add-On processes.  In the System Explorer window configuration tree, select the Power Electronics Add-On custom device, then click the Processor Assignments button under Advanced Performance section to display this dialog window.

The Processor Assignments Dialog Window and Low Latency FPGA Communication are available in VeriStand 2019 and up.


Processor assignment is managed by the Power Electronics Add-On by default.  In most cases, manual processor assignment is not required and the Processor Assignment Mode must be set to Automatic.  However, if the project contains one or more of the following, please contact OPAL-RT Support for assistance manually assigning CPU processors:

  • A custom hardware configuration consisting of two or more FPGAs
  • Additional VeriStand custom devices whose performance may conflict with the Power Electronics Add-On
  • A specific component (such as a CPU simulation model) that must execute at an increased speed, potentially at the expense of the performance of other processes


This dialog window includes the following components:

General Processor Assignment Settings
Processor Assignment Mode

Select one of the following modes: 

  • Automatic - Processors assignments are configured automatically, and all other dialog controls are disabled.  This is the default state.
  • Manual - Processor assignments can be configured manually by the users.  This model enables all dialog controls.
FPGA Communication Process 1
Processor
The index of the CPU processor on which FPGA Communication Process 1 executes. This is an indicator; the Power Electronics Add-On automatically assigns the first enabled CPU core from the System CPU Pool as the processor.
Loop Rate (us)

The loop rate of FPGA Communication Process 1, in microseconds.

FPGA Communication Process 2
Processor
The index of the CPU processor on which FPGA Communication Process 2 executes.
Loop Rate (us)

The loop rate of FPGA Communication Process 2, in microseconds.

Low Latency FPGA Communication Process
This table displays the available FPGA targets supporting Low Latency Communication. The following parameters are configurable for each FPGA target.

Processor 1

The index of the CPU processor on which the Low Latency FPGA Communication Process of the specified FPGA target executes.

For hardware configurations with two or more FPGAs, it is recommended to dedicate one CPU core per Low Latency FPGA Communication Process, and to avoid sharing it with any other process from this or another custom device.

Loop Rate (us)

The loop rate of Low Latency FPGA Communication Process of the specified FPGA target, in microseconds.
System CPU Pool Assignment

The System CPU Pool is a set of CPU cores reserved for non-high priority processes on the real time target.

Select at least one CPU core to dedicate to medium- and low-priority processes executed by the target. Avoid enabling cores reserved by either the FPGA Communication Process 2 or any of the Low Latency FPGA Communication Processes.  The first enabled CPU core from the System CPU Pool is automatically assigned to FPGA Communication Process 1.

Note that certain National Instruments embedded controllers have four available cores rather than eight.  In these cases, select from CPU cores 0 through 3.

All CPU assignment fields uses a zero-indexed convention, in which the first CPU core is represented by the number 0. Depending on the real time controller model, there are typically either four or eight cores available.
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