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IO Capabilities

This configuration requires the following FPGA boards. Please refer to the linked product page for additional information.


FPGA Board


The PXIe-7868R supports the following features:

IO Type


Analog Input

6 CH, 1MS\s, 16-bit, +/- 10V Input Signal Range, Differential

Tunable Gain, Offset, and Min/Max Saturation

Analog Output

18 CH, 1MS\s, 16-bit

User-defined mapping to Analog Outputs available with tunable Gain, Offset, and Min/Max Saturation.

  • Measurements
  • Sinewaves
  • CPU (VeriStand)
  • 6-Phase PMSM BLDC
Digital Input16 CH, 80MHz, 3.3V TTL (Connector 1)
Digital Output

32 CH Total:

  • 16 CH, 10MHz, 3.3V TTL (Connector 0)
  • 16 CH, 80MHz, 3.3V TTL (Connector 1)

User-defined mapping to Digital Outputs available with tunable Polarity.

  • CPU (VeriStand)
  • Encoders
  • PWMs
  • Digital Inputs

Refer to 7868 IO Assignation [eHSx32_6_Ph_PMSM_VDQ_IO_32DO_7868R] to see the IO assignment.

Modeling Capabilities

This configuration includes a pre-compiled firmware/bitfile which contains the following features:

⚫ = Supported (VeriStand 2019+)    ⚪ = Not Supported

In features with Low Latency Support, data is transferred between the FPGA and Real Time VeriStand Channels through the Low Latency FPGA Communication Processes. For more information related to communication processes in the Power Electronics Add-On, refer to Processor Assignments.  Note that Low Latency Support is offered in VeriStand 2019 and up.

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