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The OP5650XG is a complete simulation system, that contains a powerful target computer, a reconfigurable FPGA, and signal conditioning for up to 256 I/Os.

The design makes it easy to use with standard connectors (DB37, RJ45, SFP, and mini-BNC) without the need for input/output adaptors and allows quick connections for monitoring I/O signals.

It is designed to be used either as a desktop, shelf top, or mounted in a standard 19’’ rack.

Simulator Architecture 

The front of the chassis provides access to the target computer’s standard connectors, and monitoring interfaces and connectors, while the back of the chassis provides access to the I/O connectors, power cable, and main power switch.

The main housing is divided into two sections, each with a specific purpose:

The lower section of the chassis contains a powerful target computer that can be added to a network of simulators or can act as a standalone.

The target computer is used to run simulations built with OPAL-RT’s RT-LAB or HYPERSIM software simulation platform and includes the following features:

  • ATX motherboard
  • OPAL-RT-Linux 3.x real-time operating system
  • Intel® Xeon® Scalable Processors - 2nd Generation CPU with 4, 8 and 16 processor cores, up to 3.8GHz. See Configuration Options below.
  • 32GB of DRAM
  • 512GB SSD disk,
  • Space to install 2 PCI with risers, or 3 PCIe

The upper section contains the high-speed FPGA and the conditioning modules for up to 256 I/Os.

It includes:

  • a Xilinx® Artix®-7 FPGA programmable from the target computer via PCIe. The FPGA is used to execute models designed with the OPAL-RT RT-XSG toolbox, manage the I/O lines and execute embedded FPGA-based simulations. It exchanges data with the real-time simulations running on the target computer CPUs via the PCIe link--an 8-slot flat carrier board capable of connecting any combination of up to 8 digital and analog conditioning modules.
  • Each module controls 16 or 32 lines for a total of up to 256 I/0 lines.
  • 4 SFP ports for high-speed communication with other FPGA-based systems or with external devices. The standard communication protocols available with the OP5650XG are based on Xilinx Aurora (1 to 5 Gbps). Other protocols, such as the Gigabit Ethernet, can also be implemented.
  • These SFP ports can be used to expand the simulator’s I/O capability using OPAL-RT’s MUlti-System Expansion link (MuSE): each port can be connected to one OPAL-RT remote I/O unit (OP4520, OP5650, OP5607), effectively increasing the simulator I/O capability to a maximum of 4096 channels.
  • SFP ports not used for MuSE remain compatible with the legacy Generic Aurora link. The MuSE link is compatible with OPAL-RT boards I/O management architecture.

Note also that the Ethernet port supports only 1 Gbps Ethernet link and thus does not support 10/100 Mbps.\


These features can be represented by the diagram below :

Simulator Architecture

The OP5650XG also comes as an I/O expansion unit, the OP5650-IO-REMOTE, which connects via OPAL-RT MUlti-System Expansion link (MuSE) link to a real-time simulator.

OP5650-IO-Remote Architecture

Note

The example shown is only to illustrate how the OP5650XG is assembled.
OPAL-RT strictly prohibits users from opening the OP5650XG. Opening the unit renders the warranty null and void.

Configuration Options

The OP5650XG is available in a number of different configurations that make it easier to integrate into your environment:

Part NumberDescriptionCPUFPGA
OP5650XG-4OP5650XG - RCP/HIL Artix-7 FPGA-based Real-Time Simulator - 4 cores Intel® Xeon® 4 cores - 3.80 GHzXilinx Artix®-7
OP5650XG-8OP5650XG - RCP/HIL Artix-7 FPGA-based Real-Time Simulator - 8 cores Intel® Xeon® 8 cores - 3.80 GHzXilinx Artix®-7
OP5650XG-16OP5650XG - RCP/HIL Artix-7 FPGA-based Real-Time Simulator - 16 cores Intel® Xeon® 16 cores - 3.30 GHzXilinx Artix®-7
OP5650XG-4SOP5650XG - RCP/HIL Artix-7 FPGA-based Real-Time Simulator - 4 coresIntel® Xeon® 4 cores - 2.60GHzXilinx Artix®-7
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