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Before designing cables, OPAL-RT recommends using these guidelines: Simulator EMC cable recommendations.

J1/J2 HDB44 Connector Pinout

As explained in OP8910 Hardware Interface, both HDB44 connectors J1 and J2 share the same pin-out. The 32 digital I/O signals are routed to both J1 and J2 connectors. This allows, for example, splitting the input and output signals into two different cables.


8910

Pin

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Signal Name

D0

D2

D4

GND_iso

D8

D10

D12

NC

D16

D18

D20

GND_iso

D24

D26

D28

Pin

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Signal Name

D1

D3

D5

GND_iso

D9

D11

D13

NC

D17

D19

D21

GND_iso

D25

D27

D29

 

Pin

31

32

33

34

35

36

37

38

39

40

41

42

43

44

 

Signal Name

D7

D6

GND_iso

GND_iso

D15

D14

GND_iso

GND_iso

D23

D22

GND_iso

GND_iso

D31

D30

 

The direction of the signals D0 to D31 depend on the OP8910 assembly selected :

Part NumberDescriptionDigital In

Digital Out

OP891132 Dout LVTTL/TTL SLSC Conditioning Board
D0-D31
OP891316 Din/16 Dout LVTTL/TTL SLSC Conditioning BoardD0-D15D16-D31
OP891532 Din SLSC Conditioning BoardD0-D31

J3 Connector Pinout

GND_isoGND_iso
VBus_AVBus_B

J2 Connector Pinout


XJ2 SignalOP8910XJ2 PinXJ2 SignalOP8910XJ2 Pin
P0.0D0a1P2.0D16a7
P0.1D1b1P2.1D17b7
P0.2D2d1P2.2D18d7
P0.3D3e1P2.3D19e7
P0.4D4a2P2.4D20a8
P0.5D5b2P2.5D21b8
P0.6D6d2P2.6D22d8
P0.7D7e2P2.7D23e8
GNDGNDa3GNDGNDa9
GNDGNDb3GNDGNDb9
GNDGNDc3GNDGNDc9
GNDGNDd3GNDGNDd9
GNDGNDe3GNDGNDe9
P1.0D8a4P3.0D24a10
P1.1D9b4P3.1D25b10
P1.2D10d4P3.2D26d10
P1.3D11e4P3.3D27e10
P1.4D12a5P3.4D28a11
P1.5D13b5P3.5D29b11
P1.6D14d5P3.6D30d11
P1.7D15e5P3.7D31e11
GNDGNDa6GNDGNDa20
GNDGNDb6GNDGNDb20
GNDGNDc6GNDGNDc20
GNDGNDd6GNDGNDd20
GNDGNDe6GNDGNDe20
GNDGNDa17GNDGNDa23
GNDGNDb17GNDGNDb23
GNDGNDc17GNDGNDc23
GNDGNDd17GNDGNDd23
GNDGNDe17GNDGNDe23

XJ3 Connector Pinout


XJ3 connector

Molex connector (on standard RTI) 

XJ3 pinOP8910
HVBus_A
GGND_iso
FVBus_B
EGND_iso
DVUser_1
CGND_iso
BVUser_2
AGND_iso






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