Pour la documentation en FRANÇAIS, utilisez l’outil de traduction de votre navigateur Chrome, Edge ou Safari. Voir un exemple.

Each of the 24 pulsed output channels ( PO1:24) can be configured in analog or digital mode and with various reference voltage and can be represented by the schematic below:

Note that OC and OV signals are presently not taken into account by the FPGA module and thus not reported to the operator.

For each channel, the operator controls the output mode (open-drain or adjustable analog) from the POM Module Configuration Panel. In total, six choices of mode are available:

The default state of the output is Open (disabled).

At run-time, the operator controls the output by specifying the frequency and duty-cycle for each channel from the POM Module Run-Time Panel.

Digital mode (PO1:24EXTV1:12)

In Open drain (digital) mode, the output high level is referenced to the rail voltage that is either IGN1, ECU5V or an external voltage.

When the external voltage mode is selected, the voltage is supplied via the EXTV1-12 input lines. Since only 12 lines are available, each line is used for 2 consecutive channels, e.g. EXTV1 is used for PO1 and PO2, EXTV2 is used for PO3 and PO4.

This output stage has a resistance to ground of less than 50 milliohms and is able to dissipate a minimum of 0.01 watts. This output is able to function over the Operating Voltage range.

At run-time the value switches between 0 and ECU5V, IGN1 or External voltage at the frequency and with the duty cycle factor specified in the POM Module Run-Time Panel.

Analog mode (PO1:24, BIASV1:12)

In analog mode, the output is generated by a Digital to Analog converter. The output has a maximum peak to peak voltage of 24 V with a resolution of 0.0234V ±1% and an accuracy of 1% over the range. The output is able to drive 60 mA.

Two configuration options are available in the POM Module Configuration Panel : Adjustable AC, and Adjustable AC with BIAS. The second mode allows using the BIASV1-12 inputs to supply an external offset. Similarly to the digital External voltage pins, each BIAS input is used for two consecutive channels. For both modes, the operator sets the amplitude of the output signal, and the offset voltage value in the panel.

The internal offset voltage range of values is ± 12 volts with a resolution of .0234 V ± 1% and a 1% accuracy over the range. For the external BIAS, the range is ± 12 volts and the output stage tracks this voltage within 1 %.  

At run-time, the output signal is a bipolar signal centered around the offset voltage value, with the frequency and duty cycle factor set in the POM Module Run-Time Panel.

Frequency and Duty cycle precision

The following tables show the Marginal Frequency resolution and the frequency accuracy due to the frequency divider. However, the user should keep in mind that current hardware configuration features a Module Clock frequency of either 100 MHz with 100 ppm (0,01%) or 62,5 MHz with 30 ppm (0,003%). The crystal accuracy factor is not included in the tables below. Tables were calculated with a clock of 62.5 MHz and highlighted numbers in bold indicate characteristics over specification.

  • No labels