The OP5607 expansion unit was designed with the Xilinx VC707 Virtex-7 FPGA development board to provide additional signal conditioning to OPAL-RT simulators. The FPGA, which can be programmed either through the target computer’s PCIe or via the MUlti-System Expansion link (MuSE), is used to execute models designed with OPAL-RT RT-XSG, manage I/O lines and execute embedded FPGA-based simulations.
- Generic Aurora communication: this mode is enabled using the Generic Aurora blocks of the OPAL-RT RT-XSG toolbox. These blocks are used to exchange data with third-party devices or with other OPAL-RT systems. The data communication layer (data packing/unpacking) must be configured by the user according to the targeted application. The communication speed is configurable between 1 and 5 Gbps and the SFP transceivers must be selected accordingly.
- OPAL-RT MUlti-System Expansion link (MuSE): this mode encapsulates the Aurora protocol within a network protocol designed by OPAL-RT for inter-system communication. The communication speed is set to 5Gbps by default, but downgrades automatically to the speed of the other port, if that port is used at a lower speed for third-party device connection. The PCIe connection with the real-time simulator is not needed in this configuration. Only one SFP is used for the MuSE link, the other SFP ports remain available for the legacy Generic Aurora link.
Other protocols like the Gigabit Ethernet can also be implemented.
Note: The MuSE link is compatible with OPAL-RT Boards, OPAL-RT’s new I/O management software architecture. Restrictions to using MuSE with OPAL-RT Board software architecture may apply depending on your application and software configuration. Contact your sales representative or field application engineer to verify compatibility.