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This configuration includes a pre-compiled firmware/bitfile which contains the following features:


Additional Information

Low Latency Support

1x eHSx32 Solver

User-defined mapping to Circuit Sources available:

  • CPU (VeriStand)
  • Sinewaves
  • Dual PMSM SH
  • Analog Inputs

User-defined mapping to Circuit Switches available:

  • CPU (VeriStand)
  • PWMs
  • SPWMs
  • Digital Inputs

2x PMSM Spatial Harmonics Model
V1 implementation of the PMSM SH machine model.
Refer to Permanent Magnet Synchronous Machine Models Comparison for more information.
1x Resolver/motor

Excitation can be generated internally or assigned to any Analog Input port.

1x Encoder/motorCan be configured to simulate a Quadrature Encoder or a Hall Effect sensor.  Outputs are assignable to any Digital Output port.Analog Input Rescaling32x Waveform Acquisition Channels
- V1

1x Encoder/machine

1x Resolver/machine

32x Sinewave Generators
16x PWM Generators
12x Sinusoidal PWM Generators
Analog Output Mapping and Rescaling
18x Analog Outputs
6x Analog Inputs
16x Digital Outputs
32x Digital Inputs
32x Waveform Acquisition Channels
Telemetry Channels

⚫ = Supported (VeriStand 2019+)   ⚪ = Not Supported

In features with Low Latency Support, data is transferred between the FPGA and Real Time VeriStand Channels through the Low Latency FPGA Communication Processes. For more information related to communication processes in the Power Electronics Add-On, refer to Processor Assignments.  Note that Low Latency Support is offered in VeriStand 2019 and up.