This page includes the following components, configurable at edit-time only:
|Name||Specifies the name of the circuit model.|
|Description||Specifies a description for the circuit model.|
|Circuit Model File Path||Specifies the path to the circuit model file on disk. When a file path is added or modified, the model file is parsed and VeriStand channels are created corresponding to the Source, Switch, and Measurement components defined in the circuit model. Component configuration settings are set to their default valuesstates.|
|Reload||Parses the currently specified circuit model and updates the VeriStand channels. Components whose names have not changed retain their previously configured settings, while new or modified components are reset to the default valuesstate. Components that are no longer part of the model are removed.|
|Clear||Removes the currently loaded circuit model. When a circuit model is cleared, the corresponding Source, Switch, and Measurement sections are deleted from the Configuration Tree and all related mapping configuration settings are removed.|
|Timestep (s)||Specifies the Timestep of the circuit model. A value of 0 means the model will execute at the speed of the Minimum Timestep (s).|
|Circuit Model File Warning|
If the file at Circuit Model File Path has been modified on disk since the circuit model was last loaded, the following warning message is displayed:
Circuit model file has been modified on disk.
Click Reload to ensure that the currently loaded model is up to date with the version on disk. Reloading the model clears the warning message.
|Scenarios File Path|
Specifies the path to the Scenarios file on disk.
Creates a new Scenario template file with the name and path specified in Scenarios File Path. The specified file must have the extension .xls.
|Use Scenarios?||Enables the Scenarios feature in eHS. When enabled, the Scenario ID channel is added to the Configuration Tree.|
Minimum Timestep (s)
|Displays the smallest timestep at which the eHS Solver can simulate the circuit model. eHS will run the simulation at this timestep by default, unless a larger timestep is specified in the Timestep (s) field.|
|Number of Scenarios Used||Displays the number of Scenarios defined in the currently loaded Scenarios file.|
|Maximum Number of Scenarios||Displays the maximum number of scenarios that can be configured in the Scenarios file.|
|Refresh||Reanalyzes the circuit model file to refresh the information displayed under Model Information.|
This section includes the following custom device channels:. The value of an input channel can be modified dynamically at execution time.
|Channel Name||Type||Default Value||Description|
Specifies the index of the scenario to be simulated. Modify the value of this channel at run-time to switch between scenarios.
This channel is only available when Use Scenarios? is enabled.
The OPAL-RT electric Hardware Solver (eHS) is a floating-point solver that enables users to simulate an electric circuit on an FPGA without having to write the mathematical equations. It combines the simplicity of building electric circuit models using circuit editing software with the strength of FPGA-based simulators to solve the currents and voltages within the circuit in real-time, with a sample time below 1µs.
The eHS Solver uses Modified Nodal Analysis to generate a conductance matrix that, when solved, returns the voltage at each node of the circuit and the current in each branch. The conductance matrix of the circuit is generated independently from the state of the switches, and therefore does not need to be recomputed when a switch is opened or closed during the simulation. This is achieved through the implementation of the Pejovic method, which represents each Switch component as an impedance–a conducting switch is represented as an inductor and an open switch is represented as a capacitor.