These blocks implement a new generation of Time-Stamped Bridge (TSB) called TSB-RD, RD standing for Real Diodes. These TSB supports interpolation methods of previous generation of TSB. The high-impedance mode and rectifying mode are now implemented with real SPS diode or a combination of SPS switch and thyristors (which are enablable diode in fact). Compared with the previous generation of TSB which implemented high-impedance mode with a zero-current feedback loop, TSB-RD are generally more stable and work with RC snubber of high impedance than previous generation of TSB.
TSB-RD family of blocks is composed of the following 3-phase inverters:
- 3-level neutral-point-clamped
- 3-level T-type
Like previous generation of TSB, TSB-RD blocks supports dead-time smaller than simulation time step (as opposed to SPS inverter models).
The 2-level TSB-RD is also capable of parallel operation with firing delays between stages.
TSB-RD recommended usage with SSN
The TSB-RD are built using real SPS switches, diode and/or thyristor. All 3-phase inverters (2-level, 3-level NPC and 3-level T-type) have 9 internal SPS switches, which is close to the typical limit for pre-calculation methods in real-time systems. The TSB-RD inverters are therefore best used in conjunction with SSN and put each inverter in a unique SSN group.
2-level (left), 3-level NPC(center) and 3-level T-type inverter(right) configurations
Switch conduction resistance (Ohms): the IGBT/GTO/MOSFET conduction resistance in Ohms.
Snubber resistance (ohms): the snubber resistance in ohms.
Snubber Capacitance (F): the snubber capacitance in Farads.
Note: the snubbers are always ‘in circuit’ as they are modeled by SPS components, unlike the previous generation of TSB where snubber was in-circuit only during high-impedance mode.
Active Switch Forward Voltage (3-level NPC only): the IGBT/GTO/MOSFET forward voltage in volts.
Diode Forward Voltage (3-level NPC only): the anti-parallel diode forward voltage in volts.
Parallel TSB option (2-level only): this option enables the TSB-Rd to work in parallel. In that case, the blocks ‘Itotal’ input of all parallel TSB-RD must be fed with the sum of the ‘Iabc’ from all the TSB-RD.
Input and Output signals
Simulink connection points
g: the IGBT/GTO/MOSFET gate input signals. The order of the gate signal for phase A is indicated in Figure 1. Phase B and C are following.
Iabc: the inverter output currents in Ampere.
Itotal: the total of inverter output currents from all parallel inverters. Used only when ‘Parallel TSB option’ is enabled.
Physical Modeling connection points
A,B,C: inverter outputs for phases A,B and C.
V+, Vn, V-: DC-bus connection points. (Vn is the neutral connection point for 3-level inverters only)
Detailed examples using 2-level, 3-level NPC, and 3-level T-type inverters are available in the ARTEMiS on-line section ‘TSB-RD (New TSB with real-diodes and dead-time support, used with SSN)’.
The 2-level example is used with the ‘parallel TSB option’.
C. Dufour, J. Mahseredjian , J. Bélanger, “A Combined State-Space Nodal Method for the Simulation of Power System Transients”, IEEE Transactions on Power Delivery, Vol. 26, no. 2, April 2011 (ISSN 0885-8977), pp. 928-935