This configuration requires the following FPGA boards. Please refer to the linked product page for additional information.
The PXIe-7868R supports the following features:
6 CH, 1MS\s, 16-bit, +/- 10V Input Signal Range, Differential
Tunable Gain, Offset, and Min/Max Saturation
18 CH, 1MS\s, 16-bit
User-defined mapping to Analog Outputs available with tunable Gain, Offset, and Min/Max Saturation.
|Digital Input||32 CH, 80MHz, 3.3V TTL (Connector 1)|
16, 10MHz, 3.3V TTL (Connector 0)
User-defined mapping to Digital Outputs available with tunable Polarity.
Refer to 7868 IO Assignation [eHSx64_Dual_PMSM_VDQ_IO_7868R] to see the IO assignment.
This configuration includes a pre-compiled firmware/bitfile which contains the following features:
Low Latency Support
|1x eHSx64 Solver|
|2x PMSM BLDC Solver|
|32x Sinewave Generators||⚪|
|16x PWM Generators||⚪|
|12x Sinusoidal PWM Generators||⚪|
|18x Analog Outputs||⚪|
|6x Analog Inputs||⚪|
|16x Digital Outputs||⚪|
|32x Digital Inputs||⚪|
|32x Waveform Acquisition Channels||⚪|
⚫ = Supported (VeriStand 2019+) ⚪ = Not Supported
In features with Low Latency Support, data is transferred between the FPGA and Real Time VeriStand Channels through the Low Latency FPGA Communication Processes. For more information related to communication processes in the Power Electronics Add-On, refer to Processor Assignments. Note that Low Latency Support is offered in VeriStand 2019 and up.