The OP5700 is a complete simulation system. It contains a powerful target computer, a high-end reconfigurable FPGA, signal conditioning for up to 256 I/O lines and 16 high-speed fiber-optic SFP ports. The design makes it easy to use with standard connectors (DB37, RJ45, and mini-BNC) without the need for input/output adaptors and allows quick connections for monitoring I/O signals.

It is designed to be used either as a desktop, shelf top, or mounted in a standard 19’’ rack. The front of the chassis provides access to monitoring interfaces and connectors and the SFP sockets, while the back of the chassis provides access to the target computer’s standard connectors, I/O connectors, power cable, and main power switch.

System architecture

The main housing is divided into two sections, each with a specific purpose:

The lower part of the chassis contains the target computer that can be added to a network of simulators or can run standalone. The target computer, used to run simulations built with OPAL-RT’s RT-LAB or HYPERSIM tools, includes the following features:

The CPU configuration and the use of riser boards for PCI cards may limit the number of available slots, as described in the Hardware configuration section

The upper section contains the FPGA and the I/O conditioning modules. It includes:

Note: Restrictions to using MuSE with OPAL-RT board software architecture may apply depending on your application and software configuration. Contact your sales representative or field application engineer to verify compatibility

The figure below illustrates this architecture.

OP5700 simulator architecture

The image shown above is used to illustrate the layered and flexible product architecture.
Customers should not open the chassis unless under the strict guidance of Technical Support.
To do so may invalidate your warranty.

Configuration Options

The OP5700 is available in a number of CPU configurations that are factory configured according to the customer’s processing requirement.


Configuration Description


OP5700 RCP/HIL Virtex7 FPGA-based Real-Time Simulator - 4 cores (5U, Xeon E5, 4 Cores, 3.0 GHz, 10M, 16GB, 512GB SSD)


OP5700 RCP/HIL Virtex7 FPGA-based Real-Time Simulator - 8 cores (5U, Xeon E5, 8 Cores, 3.2 GHz, 20M, 16GB, 512GB SSD)


OP5700 RCP/HIL Virtex7 FPGA-based Real-Time Simulator - 16 cores (5U, Xeon E5, 2x8 Cores, 3.2 GHz, 2x20M, 2x16GB, 512GB SSD)


OP5700 RCP/HIL Virtex7 FPGA-based Real-Time Simulator - 32 cores (5U, Xeon E5, 2x16 Cores, 2.3 GHz, 2x40M, 2x16GB, 512GB SSD)

The OP5700 is built with the same FPGA and I/O architecture as the OP5607 I/O expansion chassis (OP5600 family of products), therefore the FPGA programming files (bitstreams) are fully compatible.

System Interconnection Details

There are two standard modes of operation available for the SFP ports, both based on the Xilinx Aurora communication protocol:

The MuSE mode is selected in the RT-XSG block by setting the synthesis manager architecture option to <remote>. In this mode, the unit must be connected to another OPAL-RT system that is connected in central mode, and it then becomes a remote expansion unit (similar to an OP4520 or OP4200).