The OP5607 expansion unit was designed with the Xilinx VC707 Virtex-7 FPGA development board to provide additional signal conditioning to OPAL-RT simulators. The FPGA, which can be programmed either through the target computer’s PCIe or via the MUlti-System Expansion link (MuSE), is used to execute models designed with OPAL-RT RT-XSG, manage I/O lines and execute embedded FPGA-based simulations.

The combination of this high-end FPGA, with a high number of I/O lines (up to 256), and high-speed connectivity for communication with the OPAL-RT simulator and with third-party units under test (UUT), makes the OP5607 perfectly suited to complex or I/O intensive simulations.

Features

System Overview 

The OP5607 comes in two versions: the OP5607-IO-PCIe which connects to the real-time simulator via a PCIe link, and the OP5607-IO-REMOTE, which uses SFP transceivers and an optical cable to connect to the simulator via the MuSE link.

The figure below gives a graphical overview of both options.

OP5607 Architecture

SFP Interconnection Details

The sixteen SFP sockets allow interconnection with other OPAL-RT chassis or external devices, like amplifiers or MMC controllers. The standard communication protocols available with the OP5607 are based on Xilinx Aurora (1 to 5 Gbps). 

There are two standard modes of operation available for the SFP ports, both based on the Xilinx Aurora communication protocol:

Other protocols like the Gigabit Ethernet can also be implemented.

Note: The MuSE link is compatible with OPAL-RT Boards, OPAL-RT’s new I/O management software architecture. Restrictions to using MuSE with OPAL-RT Board software architecture may apply depending on your application and software configuration. Contact your sales representative or field application engineer to verify compatibility.