Waveforms allow users to view selected simulation signals at higher speeds and with better resolution than that offered by custom device channels. Custom device channels perform single-point acquisition, a non-buffered operation that occurs at the rate at which the Real-Time CPU runs. Waveforms, on the other hand, read and stream FPGA-generated data at rates faster than the Real-Time CPU.
In the System Explorer window configuration tree, expand the Power Electronics Add-On custom device and select Circuit Model >> Waveforms to display this page. The page is populated with a list of the Waveforms available in the selected Hardware Configuration. Simulated signals can be mapped to each Waveform to allow them to be viewed at a higher resolution during the simulation.
For each Waveform, the following mapping options are available:
Filters the list of available elements to be mapped to the waveform channel. The available options are defined by the selected Hardware Configuration, however it is typical to see the following options by default:
|No signal is mapped to the Waveform.|
|eHS Measurements made in the circuit model. In the Element dropdown, select the name of the measurement to map.|
|Output channels of the Machine Model. In the Element dropdown, select the name of the channel to map.|
|Analog Input channels of the PXI card. In the Element dropdown, select the index of the AI channel to map.|
The name or index of the channel to be mapped to the Waveform. The options available in this dropdown depend on the selected Source.
|Sample Rate (S/s)||Sample rate of the data acquisition performed on the FPGA signals by the waveform engine. This Sample Rate is per channel, and applies to all the Waveform channels defined. See Waveform Data Transfer and Streaming Rate for more information.|
The Waveforms section of the Configuration Tree is populated with a list of Waveform channels corresponding to each of the 32 Waveforms available in the Hardware Configuration. Use these tree items to display the mapped signals in Waveform Graphs in the VeriStand Workspace, or in Charts in the VeriStand Editor. More information about this process can be found in How to Display Simulated Signals using Waveforms.
As the simulation executes, data generated on the FPGA is sampled by the waveform engine at the user-specified Sample Rate, then streamed to one or more of the 32 Waveform channels on the real time CPU. Each individual channel is sampled at the full Sample Rate. Because the FPGA executes much faster than the acquisition rate of the waveform engine, the data is first decimated on the FPGA and subsequently stored in an FPGA FIFO. The values stored in the FIFO are transferred over the PXI backplane to a real time buffer on the CPU, then to the VeriStand Waveform channels. All data transfer occurring after the FPGA decimation is lossless.
The maximum achievable Waveform Sample Rate is dependent upon the characteristics of the system, although rates of up to 290,000 Samples/second have been achieved on both Linux and PharLap systems in all supported versions of VeriStand. The number of configured Waveform mappings does not affect the maximum achievable Sample Rate; all 32 Waveform channels are transferred at all times, even if they have not been mapped to a Source.
How to Display Simulated Signals using Waveforms
How to Log Waveform Data to a File