A simple closed-loop SPWM frequency and modulation index controller model was developed for this example. It has been compiled into .dll and .so files for execution on both Phar Lap and Linux RT targets, respectively.  The controller model is configured to run on the Real Time CPU and will be executed by the VeriStand Engine.  Data is routed from the CPU simulation (local controller) to the FPGA simulation (eHS, SCIM model) using the VeriStand System Configuration Mappings.

Local Controller File Path: <Public Documents>\National Instruments\<NI VeriStand 20xx>\Examples\OPAL-RT\Power Electronics Add-On\Dual PMSM VDQ Local Control\Local Controller

Exploring the Local Controller

InportDefault Value
Dclink0
DesiredSpeedRPM0
ModIndexLookup


20110
100298
200525
50025
800830
1000830
1500830
2000830
2500830
3000830


Poles3
RampRate10



Exploring the Mappings to and from the Local Controller

The VeriStand System Configuration Mappings are used to route signals between the local controller and the other model components simulated on the FPGA. 

SourcesDestinations
Controller/User Channels/Supply VoltageController/Custom Device/OPAL-RT Power Electronics Module/Circuit Model/Signal Generators/Sinewave Generators/SWG Generator 0/Amplitude
Controller/User Channels/Supply VoltageController/Custom Device/OPAL-RT Power Electronics Module/Circuit Model/Signal Generators/Sinewave Generators/SWG Generator 1/Amplitude
Controller/User Channels/Supply VoltageController/Custom Device/OPAL-RT Power Electronics Module/Circuit Model/Signal Generators/Sinewave Generators/SWG Generator 2/Amplitude
Controller/Simulation Models/Models/Speed_Control/Outports/InverterFrequencyRefController/Custom Device/OPAL-RT Power Electronics Module/Circuit Model/Signal Generators/SPWM Generators/SPWM Frequency Generators/SPWM Frequency Engine 0
Controller/Simulation Models/Models/Speed_Control/Outports/ModIndexRef Controller/Custom Device/OPAL-RT Power Electronics Module/Circuit Model/Signal Generators/SPWM Generators/SPWM Carrier/Modulation Index