A simple closed-loop SPWM frequency and modulation index controller model was developed for this example. It has been compiled into .dll and .so files for execution on both Phar Lap and Linux RT targets, respectively.  The controller model is configured to run on the Real Time CPU and will be executed by the VeriStand Engine.  Data is routed from the CPU simulation (local controller) to the FPGA simulation (eHS, SCIM model) using the VeriStand System Configuration Mappings.

Local Controller File Path: <Public Documents>\National Instruments\<NI VeriStand 20xx>\Examples\OPAL-RT\Power Electronics Add-On\Dual PMSM VDQ Local Control\Local Controller

Exploring the Local Controller

• In the Configuration Tree, expand Controller >> Simulation Models >> Models. Click Volts Per Hertz Controller to view the model file information.
• By default, the .so file is loaded for execution on a Linux RT target.  To run the example on a Phar Lap target, click the Browse Simulation Model button in the Menu bar and select VoltPerHertzController.dll from the Local Controller File Path listed above.
• In the Configuration Tree, expand Volt Per Hertz Controller >> Inports and confirm that all inports have been configured as shown in the table below.
• Click Save.
  

Exploring the Mappings to and from the Local Controller

The VeriStand System Configuration Mappings are used to route signals between the local controller and the other model components simulated on the FPGA. 

• In the VeriStand System Explorer window, navigate to Tools >> Edit Mappings in the Menu bar.
• Confirm that the mappings are configured as shown in the table below.