This Hardware Configuration has been archived and should not be used in new projects. Please contact OPAL-RT Support for more information.
This configuration requires the following FPGA boards. Please refer to the linked product page for additional information.
The PXIe-7868R supports the following features:
6 CH, 1MS\s, 16-bit, +/- 10V Input Signal Range, Differential
Tunable Gain, Offset, and Min/Max Saturation
18 CH, 1MS\s, 16-bit
User-defined mapping to Analog Outputs available with tunable Gain, Offset, and Min/Max Saturation.
|Digital Input||32 CH, 80MHz, 3.3V TTL (Connector 1)|
16, 10MHz, 3.3V TTL (Connector 0)
User-defined mapping to Digital Outputs available with tunable Polarity.
Refer to 7868 IO Assignation [eHSx64_IM_IO_7868R] to see the IO assignment.
This configuration includes a pre-compiled firmware/bitfile which contains the following features:
1x eHSx64 Solver
User-defined mapping to Circuit Sources available:
User-defined mapping to Circuit Switches available:
|1x ACIM Constant Parameter Model||Refer to ACIM Section (Archived) for more information.|
The excitation signal for the resolver is directly connected to the AIO channel. This connection is not assignable. In addition, the excitation signal must be scaled appropriately such that it has an amplitude of -1V to 1V.
|1x Encoder||Assignable to any DO port|
|1x Hall Effect Sensor||Assignable to any DO port|
|32x Sinewave Generators|
|16x PWM Generators|
|12x Sinusoidal PWM Generators|
|Analog Output Mapping and Rescaling|
|Analog Input Rescaling|
|32x Waveform Acquisition Channels|